1. Field of the Invention
The present invention relates generally to a NOR flash memory device. More particularly, the invention relates to a NOR flash memory device having multi-level memory cells, and a method of sensing the logic state of the multi-level memory cells.
A claim of priority is made to Korean Patent Applications Nos. 2004-106388 and 2004-106390, both filed on Dec. 15, 2004, the disclosures of which are hereby incorporated by reference in their entirety.
2. Description of Related Art
NOR flash memory is a popular form of non-volatile data storage used in various portable electronic devices such as cell phones, personal digital assistants (PDAs), removable memory cards, and so forth. NOR flash memory is particularly well suited for applications requiring high data access speed. For example, NOR flash is often used to store program code. In contrast, NAND flash memory is often used for mass data storage due to its relatively slower data access speed and its lower price.
A flash memory cell comprises a source and a drain, both doped with N+type impurities, and a channel formed in a P-type semiconductor substrate between the source and the drain. The flash memory cell further comprises a floating gate formed over the channel, and a control gate formed over the floating gate. The floating gate is separated from the channel by a thin oxide insulating layer, and the control gate is separated from the floating gate by a thin oxide insulating layer.
A flash memory cell is programmed by placing a high voltage (e.g., 12V) on the control gate while generating a current across the channel region, e.g., by placing 6V on the drain region and connecting the source region to ground. The combination of the high voltage and the current causes some electrons in the current to be transferred to the floating gate via “hot-electron injection.”
A flash memory cell is read by placing a voltage of about 4.5 or 5V on the control gate, a voltage of about 1V on the drain, and a voltage of about 0V on the source. Under these conditions, current may or may not flow across the channel depending on how many electrons are stored in the floating gate. Accordingly, the logic state of the memory cell can be detected by determining how much current flows across the channel.
Where the memory cell is programmed, the electrons transferred to the floating gate partially cancel out an electrical field generated by the voltage on the control gate, and therefore relatively little current flows through the channel. In other words, the electrons on the floating gate effectively elevate the threshold voltage of the memory cell so that it does not turn on. On the other hand, where the memory cell has not been programmed, current readily flows through the channel because the 4.5 or 5V on the control gate is above the threshold voltage of the memory cell when it is not programmed.
Like most memory devices, NOR flash memory preferably stores a large amount of data in a small area. One way to increase the amount of data stored in an area of a NOR flash memory device is to increase the number of memory cells in the area. Yet another way to increase the amount of data stored in an area of a NOR flash memory device is to increase the number of bits stored in each memory cell.
A memory cell storing more than one bit of data is referred to as a “multi-level cell,” and a device containing multi-level cells is called a “multi-level cell device.” For instance, a memory cell storing 2 bits has four “levels” or logic states: “11”, “10”, “01”, and “00”. The four states of a 2-bit flash memory cell can be distinguished by measuring the amount of current that flows through the channel during a read operation rather than simply detecting presence or absence of current. The flash memory cell can be programmed to one of the four states by placing different amounts of electrons on the floating gate.
In a conventional multi-level cell device, the logic state of each multi-level cell is measured by a set of sense amplifiers adapted to detect and amplify differences between various reference currents and a channel current flowing through the channel of the multi-level flash cell. For instance, the 2-bit flash memory cell is generally read by generating three (3) reference currents and comparing each of the reference currents to the channel current using three respective sense amplifiers. The relationship between the channel current and the three reference currents is then used to determine the logic state of the multi-level flash cell. For instance, if the channel current is larger than all three of the reference currents, then the multi-level flash cell has the logic state “11”. If the channel current is larger than two of the reference currents, then the multi-level flash cell has the logic state “10”, and so forth.
Unfortunately, it is extremely difficult to form each of the sense amplifiers to have the same characteristics. Due to mismatches in the sense amplifier characteristics, it is difficult to sense small differences in the current flowing through the channel of the NOR flash memory device.